Once formation of semiconductor devices and interconnects on a semiconductor wafer (substrate) is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting on a circuit board. A package is a supporting element for the semiconductor chip that provides mechanical protection and electrical connection to an upper level assembly system such as the circuit board. One typical packaging technology is Controlled Collapse Chip Connection (C4) packaging, which employs C4 balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate. The packaging substrate may then be assembled on the circuit board.
Thus, the packaging substrate facilitates formation of an electrical link between the semiconductor chip and a system board of a computer. A semiconductor chip is mounted on a die foot print area located on a top surface of the packaging substrate. The die foot print area contains C4 pads on which a semiconductor chip may be attached by C4 bonding.
A typical semiconductor chip employing a packaging substrate may comprise about 5,000 input/output nodes. Each of these nodes is electrically connected to a C4 pad on a top surface of the semiconductor chip in a two dimensional array. Typical two dimensional array configurations for the C4 pads include 4 on 8 configuration, which employs C4 solder balls having a diameter of 4 mils (approximately 100 microns) and a pitch of 8 mils (approximately 200 microns) in a rectangular array, and 3.0 on 6 configuration, which employs C4 solder balls having a diameter of 3.0 mils (approximately 75 microns) and a pitch of 6 mils (approximately 150 microns) in a rectangular array. Thus, more than 5,000 C4 solder balls may be formed on the semiconductor chip, which may be typically about 2 cm×2 cm in size.
Use of lead free-alloys for C4 balls is increasing to reduce environmental impacts. Plating or mold-transfer processes may be employed to form the C4 balls. Typical prior art alloy compositions for lead-free C4 balls include a Sn—Ag alloy (with an atomic concentration of Ag in the range from about 0.1% to about 2.3%, and typically from about 0.5% to about 1.1%, the balance being Sn), a Sn—Cu alloy (with an atomic concentration of Cu in the range 0.5% to 0.7%, the balance being Sn), a Sn—Ag—Cu (atomic concentration of Ag in the range from about 0.1% to about 2.3%, and typically from about 0.5% to about 1.1% and atomic concentration of Cu in the range 0.5% to 0.7%, the balance being Sn). These alloys are therefore Sn-rich, i.e., contains Sn at an atomic concentration above 95%.
Upon solidification, the prior art alloy materials tend to form large grains in the lead-free C4 balls. The number of grains in the solidified lead-free C4 balls is correspondingly small, e.g., typically from 1 to 5, and more typically from 1 to 3. The tendency to form very few grains, e.g., from 1 to 3 grains within the entirety of a solidified lead-free C4 ball is further exacerbated by a slow cool down process that is employed to reduce the transient stresses on the chip which would otherwise arise, i.e., if the lead-free C4 balls were rapidly quenched. Such slow cool down processes are increasingly required to mitigate back-end-of line (BEOL) stresses such as structural back end damage resulting in separation of the C4 balls from a semiconductor chip. This phenomenon is sometimes referred to as “white bumps” because when the chip is scanned using ultrasound waves, damaged areas under C4s which are areas of delamination, show up as white spots rather than as dark spots. Dark spots typically correspond to areas without delamination or other damage in the vicinity of the C4.
The tendency to form very few grains is further exacerbated by recent trends in the composition of the prior art alloy materials, in which the alloy composition is moving closer to pure Sn for reasons related to BEOL stress build-up. In this case, pure metals provide lower yield strength than an alloy of that metal with other metals. The lower the content of the other metals, the lower the yield strength of the alloy. For example, a Sn—Ag alloy containing Ag at an atomic concentration of 0.5% has a lower yield strength than a Sn—Ag alloy containing Ag at an atomic concentration of 1.1%. The low yield strength helps reduce the effective stress on the semiconductor chip during the reflow by accommodating stress by deformation within the lead-free C4 ball. However, as the alloy approaches pure Sn in composition, grain growth occurs more readily resulting in fewer grain boundaries under similar reflow conditions. This is disadvantageous to the stress mitigation in the lead-free C4 balls during subsequent thermal cycling since fewer grain boundaries are available for grain boundary sliding, which is a mechanism to mitigate stress in the lead-free C4 balls.
Further, additional thermal processes that the semiconductor chip is subjected to, including ball grid array (BGA) join, BGA join rework if applicable, card join, card join rework if applicable, lid join, lid join rework if applicable, facilitate grain growth in the lead-free C4 ball. This tendency is more pronounced in the lead-free C4 balls, which are Sn-based, than in lead-based C4 balls due to the differences in the homologous temperatures.
Thus, formation of a small number of grains in the lead-free C4 ball, e.g., 1 or 2, creates more stress on the semiconductor chip than formation of a large number of grains in the lead-free C4 ball, all other parameters for the C4 balls being equal. This is because grain boundary sliding is not possible with 1 grain to provide stress alleviation, while a many-grained C4 ball containing, for example, 5 or 10 grains per C4 ball, is conducive to stress-mitigation within the C4 ball so that less stress is transmitted into the semiconductor chip thereupon.
In view of the above, there exists a need for an alloy composition that induces multiple grains per C4 ball without requiring modification in any processing temperature or conditions, structures for effecting the same, and methods for effecting the same.